1. Field of the Invention
The present invention relates generally to a register access method, and structure. Specifically, the present invention relates to a register access architecture that does not require use of a bus clock signal to synchronize its operation to a cpu/mpu unit.
2. Description of the Related Art
Typically, accessing a register block on a cpu or mpu bus requires a bus clock to synchronize the register block with the cpu/mpu. The bus clock, which is typically provided by the cpu/mpu and whose cycle period is thus equivalent to a cpu/mpu operation cycle, is also needed to allocate additional time in predetermined clock cycle increments to the register block, which typically requires more time than is provided by one bus clock cycle (i.e. one operation cycle of the cpu/mpu) to implement a write, or read, operation.
Various method of synchronizing a register block, or memory block, to the cpu/mpu operation cycle are known. In one implementation, the cpu/mpu may issue a memory request signal to the register block, along with the request for a read or write operation. The cpu/mpu then monitors its bus until the register block responds with an acknowledge signal letting the cpu/mpu know that the register block is ready to proceed with the requested operation. The register block typically requires multiple bus clock cycles before responding with the acknowledge signal. In this case, the amount of bus clock cycles that the cpu/mpu is made to wait is indefinite.
In an alternate approach, a wait line is used to notify the cpu/mpu that the requested read or write operation cannot be implemented yet. The cpu/mpu does not know how long the wait time will be, and must therefore constantly monitor the wait line to determine when it may stop waiting and proceed with the requested operation.
As it is known, the bus includes multiple control lines carrying various signals, including a chip select signal on a first line and a read/write command signal on a second line, which is typically set to a logic high to indicate a read operation request and set to a logic low to indicate a write operation request. Typically, the register block monitors these two bus control lines, and when the chip select signal is sampled as active, the command signal (read or write) is sampled to determine if the current cycle is a read cycle or write cycle. The register block then asserts a wait signal on the wait line to let the cpu/mpu know when it may accept data or provide data. The wait signal is issued for an indefinite time, as deemed necessary by the register block.
Typically, the cpu/mpu samples the wait signal from the register block at predetermined times during each subsequent bus clock cycle until the wait signal is negated. In essence, the wait signal lets the cpu/mpu know when the register block can accept data (for a write operation) or provide data (for a read operation), and thereby effectively lengthen the operation cycle until the register block can finish processing the requested data transfer. Generally, once the cpu/mpu samples the wait signal as inactive, i.e. negated, it can then finish the write/read operation cycle during the next bus clock cycle by de-asserting the chip select signal and/or the command signal.
Thus, the cpu/mpu and register block typically follow a request-and-respond sequence to transfer data between themselves. This results in lower than optimal data transfer rate since each data transfer sequence requires multiple bus cycles. Additionally, the cpu/mpu must allocate resources to monitoring its bus for an appropriate wait response from the register block.